KiCad to JLCPCB: Generate Gerbers, BOM & CPL Files
Export production-ready Gerber, BOM, and CPL files from KiCad 8 for JLCPCB PCB assembly. This step-by-step tutorial covers DRC validation, correct layer mapping, drill file generation, JLCPCB-format BOM and component placement exports, and the online Gerber viewer verification workflow that gets your custom ESP32 or sensor board manufactured without revision.
What You Need
Step-by-Step Instructions
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Step 1 Open Your Completed KiCad Project and Verify the Design
Open your KiCad 8 project (.kicad_pro) and ensure both the schematic and PCB layout are saved and synchronized. Click the "Update PCB from Schematic" button (F8) in the PCB editor to confirm there are no unresolved changes between the two files. Any mismatches at this stage will propagate into incorrect manufacturing files.
Verify your board outline is a closed polygon on the Edge.Cuts layer. JLCPCB rejects files with open board outlines or missing edge cuts. Check that all components have footprints assigned — open the schematic editor, run Tools > Edit Symbol Fields, and scan the Footprint column for any empty entries. Missing footprints mean missing pads on the PCB, which means components cannot be placed during assembly.
Confirm your design rules match JLCPCB's manufacturing capabilities. For their standard process: minimum trace width is 0.127mm (5 mil), minimum clearance is 0.127mm, minimum via drill is 0.3mm, and minimum via annular ring is 0.13mm. For 2-layer boards, the standard stackup is 1.6mm FR-4 with 1oz copper. Set these values in Board Setup > Design Rules > Net Classes if you have not already. Running DRC against tighter constraints than the fab house requires wastes time chasing false violations.
Tip: Save a backup of your project folder before generating output files. KiCad's File > Archive Project creates a .zip snapshot you can revert to if something goes wrong during export. -
Step 2 Run Design Rule Check (DRC) and Fix All Errors
In the PCB editor, open Inspect > Design Rules Checker (or press the DRC button in the toolbar). Click "Run DRC" with all checks enabled: clearance, track width, via size, copper zones, unconnected nets, and courtyard overlaps. JLCPCB will reject boards with physical DRC violations even if they pass electrical checks.
Fix all errors before proceeding. The most common DRC failures are: unconnected nets (a trace or via is missing), clearance violations between copper features (traces too close together or to board edge), and courtyard overlaps (two component footprints physically colliding). Unconnected nets are the most dangerous — they produce boards with open circuits that do not work.
Warnings are less critical but worth reviewing. Silkscreen-over-pad warnings mean text overlaps solder pads, which can interfere with soldering. Minimum annular ring warnings on vias mean your vias are at the edge of JLCPCB's capability and may have reliability issues. A clean DRC with zero errors and zero warnings is the gold standard.
After fixing all issues, run DRC again to confirm a clean pass. Some fixes introduce new violations — for example, moving a trace to fix a clearance error might create a new clearance violation elsewhere. Iterate until the DRC report shows zero errors.
Tip: Enable the "Test for parity between schematic and board" option in DRC settings. This catches components that exist in the schematic but were accidentally deleted from the PCB layout — a surprisingly common mistake when rearranging boards. -
Step 3 Plot Gerber Files with Correct Layer Mapping
Open File > Plot in the PCB editor. This is the Gerber generation dialog. Set the output directory to a subfolder like "gerbers" — keeping manufacturing files separate from your project files prevents accidental edits.
Select these layers for a standard 2-layer board: F.Cu (front copper), B.Cu (back copper), F.Paste (front solder paste stencil), B.Paste (back solder paste stencil), F.SilkS (front silkscreen), B.SilkS (back silkscreen), F.Mask (front solder mask), B.Mask (back solder mask), and Edge.Cuts (board outline). For 4-layer boards, add In1.Cu and In2.Cu. Missing any of these layers results in manufacturing defects — no solder mask means exposed copper that will oxidize and short.
Configure the plot settings: format must be Gerber (the default). Set coordinate format to 4.6 (4 integer digits, 6 decimal digits) — this gives 0.001mm resolution, which is JLCPCB's expected format. Check "Use Protel filename extensions" — this maps layers to the .GTL, .GBL, .GTS, .GBS naming convention that JLCPCB's parser recognizes automatically. Uncheck "Exclude PCB edge layer from other layers" only if your board outline must appear on copper layers (rare).
Check "Plot reference designators" under silkscreen options — these labels (R1, C1, U1) help during manual inspection and debugging. Uncheck "Plot footprint values" unless you want component values printed on the board. Click "Plot" to generate all Gerber files in your output directory.
Tip: JLCPCB also accepts KiCad's native .kicad_pcb files directly through their online upload tool. However, generating explicit Gerbers gives you a verification step and works with every PCB manufacturer, not just JLCPCB. -
Step 4 Generate Drill Files
Still in the Plot dialog, click "Generate Drill Files" (or open it separately from File > Fabrication Outputs > Drill Files). Drill files define every hole on your board — vias, through-hole component pins, mounting holes, and any slots or cutouts.
Set the drill file format to Excellon. Set the drill units to millimeters and use the same coordinate format as your Gerbers (4.6). Select "Minimal header" and "PTH and NPTH in single file" — JLCPCB handles both plated through-holes and non-plated holes from a combined file. Some manufacturers require separate files, but JLCPCB's parser splits them automatically.
Check "Drill Map" and set its format to Gerber — this generates a visual drill map you can overlay on your Gerbers to verify hole positions. Click "Generate Drill File" to create the .drl file in the same output directory as your Gerbers.
Open the drill map alongside your Gerber files to spot-check that via locations match pad locations and mounting holes align with the board outline. A misaligned drill file — usually caused by different coordinate origins between the PCB and drill export — produces boards where vias miss their pads entirely. If the drill map looks offset, set both the Gerber plot and drill file to use the same origin: either "Absolute" or "Drill/place file origin" (set the origin marker in the PCB editor with Place > Drill/Place Origin).
Tip: Count the total number of unique drill sizes in the drill file summary. JLCPCB charges extra for boards with more than 10 unique drill sizes. Standardize your via sizes to reduce drill count — most designs need only 0.3mm and 0.4mm drill diameters. -
Step 5 Export BOM in JLCPCB Format
JLCPCB's assembly service requires a BOM (Bill of Materials) in a specific CSV format with these columns: Comment (component value), Designator (reference designator), Footprint (package type), and LCSC Part Number. The LCSC part number is critical — it maps each component to JLCPCB's parts library, which they source from LCSC Electronics.
KiCad 8 has a built-in BOM exporter, but its default output does not include LCSC numbers. The cleanest workflow is to add LCSC part numbers as custom fields in your schematic symbols. Open the schematic, select Edit > Symbol Fields Table, add a column called "LCSC" (or "JLCPCB Part#"), and fill in the part number for every component. You can search LCSC part numbers at jlcpcb.com/parts or lcsc.com — for example, a 10uF 0805 ceramic capacitor might be C15850, and an ESP32-C3-MINI-1 module is C2838502.
Once all LCSC fields are populated, generate the BOM from the schematic editor: Tools > Edit Symbol Fields Table > Export as CSV. Format the CSV to match JLCPCB's expected columns. Alternatively, use the KiCad JLCPCB plugin (available in the KiCad Plugin and Content Manager) which exports directly in the correct format with a single click.
A typical 10-component ESP32 sensor board BOM includes: the ESP32 module (1 unit), voltage regulator (1), USB-C connector (1), 4-6 decoupling capacitors, 2-3 resistors, and a sensor IC. At JLCPCB's economic assembly pricing, basic components (resistors, capacitors) cost $0.001-0.01 each, while extended parts like ESP32 modules cost their LCSC price plus a $3.00 extended component fee.
Tip: Use JLCPCB's "Basic Parts" library whenever possible — these components are pre-loaded on their pick-and-place machines and have no extended component surcharge. Basic parts cover 0402-0805 resistors, capacitors, and common diodes. Extended parts add $3 per unique part number to your order. -
Step 6 Generate Component Placement (CPL) File
The CPL (Component Placement List) file tells JLCPCB's pick-and-place machine the exact X/Y position and rotation of every SMD component on the board. In KiCad 8, generate this from File > Fabrication Outputs > Component Placement (.pos file).
Set the output format to CSV, units to millimeters, and select "SMD only" (through-hole components are hand-soldered, not placed by machine). Generate the file — KiCad outputs columns for Reference, Value, Package, PosX, PosY, Rot, and Side.
JLCPCB expects these column headers: Designator, Val, Package, Mid X, Mid Y, Rotation, Layer. The column mapping is straightforward but the names must match exactly. Rename the headers in a text editor or spreadsheet: Ref → Designator, PosX → Mid X, PosY → Mid Y, Rot → Rotation, Side → Layer. The Layer column should contain "top" or "bottom" (JLCPCB's standard assembly is top-side only; bottom-side assembly costs extra).
The most common CPL issue is rotation offsets. JLCPCB's component library may define pin 1 orientation differently from KiCad's footprints. When you upload the CPL, use JLCPCB's online component placement viewer to visually verify that every IC, connector, and polarized component has the correct rotation. Fix offsets by adding or subtracting 90/180/270 degrees in the Rotation column. For a 10-component board, expect to correct 1-3 rotation values manually.
Tip: The KiCad JLCPCB Tools plugin (installable from Plugin and Content Manager) generates both BOM and CPL files in the exact format JLCPCB expects, with correct column headers and automatic rotation offset correction for common components. It saves 10-15 minutes per export cycle. -
Step 7 Upload to JLCPCB and Verify in the Online Gerber Viewer
Zip all files in your gerbers output directory: the .GTL, .GBL, .GTS, .GBS, .GTO, .GBO, Edge.Cuts, and .drl files. Do not include the BOM or CPL in this zip — those are uploaded separately. Go to jlcpcb.com, click "Order Now", and upload the zip file.
JLCPCB's Gerber viewer parses and renders your board within seconds. Verify each layer visually: front copper should show all traces and pads, back copper should show the ground plane or back-side traces, solder mask should have openings over every pad, and silkscreen should be readable without overlapping pads. Check the board dimensions displayed — they should match your design. A 50x50mm board at JLCPCB's standard pricing costs $2-4 for 5 pieces.
Click through each layer using the layer toggle buttons. Pay special attention to the drill layer overlay — every via and through-hole pad should have a drill mark centered on it. If drills appear offset, go back and regenerate with matching coordinate origins. Check the board outline on Edge.Cuts — internal cutouts and slots should appear correctly.
If you ordered assembly, click "SMT Assembly" in the order options. Upload your BOM CSV and CPL CSV. The system matches LCSC part numbers from your BOM to their inventory and shows component availability, pricing, and stock levels. Out-of-stock parts are flagged — you can substitute alternatives or remove them for hand-soldering later. The CPL viewer shows each component's position and orientation on the board — review every IC and polarized component carefully.
Tip: JLCPCB often has coupons for new users — typically $5-8 off assembly orders. Check their home page banner before placing your order. For prototype quantities (5-10 boards), economic PCBA with basic parts often costs less than buying the components separately from DigiKey. -
Step 8 Select Options and Place Your Order
Configure the PCB fabrication options. For prototypes, the standard settings work well: 2-layer, 1.6mm FR-4, 1oz copper, HASL (Hot Air Solder Leveling) surface finish, green solder mask. HASL is the cheapest surface finish and fine for hand-soldering and prototyping. If your board has fine-pitch components (0.5mm pitch QFN or BGA packages), upgrade to ENIG (Electroless Nickel Immersion Gold) for flatter pads — ENIG adds about $5-12 to a small board order.
For the assembly options, choose between Economic PCBA and Standard PCBA. Economic PCBA costs roughly $8-15 setup plus per-component charges and has a 5-7 business day turnaround. Standard PCBA costs more but supports both sides of the board, offers faster turnaround (3-4 days), and handles more complex assemblies. For a first prototype with 10 SMD components on one side, Economic PCBA typically totals $20-35 for 5 assembled boards.
Review the order summary carefully. The total breaks down into: PCB fabrication (usually $2-7 for 5 small boards), component costs (LCSC prices for each part), assembly fee (setup + per-placement charges), and shipping. JLCPCB's global standard shipping runs $5-12 with 7-15 day delivery; DHL Express is $15-25 with 3-5 day delivery.
After placing the order, JLCPCB's engineering team reviews your files within 1-2 hours during business hours (China Standard Time). They flag issues like insufficient clearance near board edges, missing solder mask openings, or component footprint mismatches. Respond to any engineering queries through their order page messaging system. Production starts after review approval — typical lead time is 2-3 days for PCB fabrication plus 2-5 days for assembly.
Tip: Order 5 boards even if you only need 1-2. JLCPCB's minimum quantity is 5 for most board sizes, and the per-board cost difference between 2 and 5 is negligible. The extras give you spares for rework, testing, or gifting to other makers.
Frequently Asked Questions
What KiCad version works best with JLCPCB's file format?
KiCad 8 (current stable release) works perfectly with JLCPCB. Its Gerber output with Protel filename extensions and Excellon drill format is exactly what JLCPCB's parser expects. KiCad 7 also works, though the menu locations for some export dialogs differ slightly. Avoid KiCad 5 or earlier — their Gerber output uses older naming conventions that require manual renaming.
Can I upload the .kicad_pcb file directly instead of Gerbers?
Yes, JLCPCB accepts native KiCad .kicad_pcb files through their web uploader. However, generating Gerbers is recommended because it gives you a verification step (you can inspect the Gerber files in a viewer before uploading), and the same Gerber files work with any PCB manufacturer — not just JLCPCB.
How do I find LCSC part numbers for my BOM?
Search at jlcpcb.com/parts or lcsc.com using the component value and package size (e.g., '10uF 0805 capacitor'). Filter by 'Basic Parts' to avoid the $3 extended component surcharge. For ICs and modules, search by the exact manufacturer part number. The KiCad JLCPCB Tools plugin also integrates LCSC search directly into the schematic editor.
Why are my component rotations wrong in JLCPCB's placement viewer?
KiCad and JLCPCB define pin 1 orientation differently for many component packages. JLCPCB's viewer shows how their pick-and-place machine will orient each part. Correct rotation offsets manually in the CPL CSV file by adding or subtracting 90-degree increments. The KiCad JLCPCB Tools plugin includes a rotation offset database that fixes most common packages automatically.
What is the cheapest way to get assembled PCBs from JLCPCB?
Use Economic PCBA with all Basic Parts on one side of the board. A 50x50mm 2-layer board with 10 basic SMD components (resistors, capacitors, common ICs) typically costs $20-35 total for 5 assembled units including shipping. Minimize unique extended part numbers — each one adds a $3 surcharge. Design with 0402 or 0805 passives from the Basic Parts library.
Should I include a ground plane on my 2-layer board?
Yes. A solid ground plane on the back copper layer (B.Cu) provides a low-impedance return path for signals, reduces EMI, and improves thermal dissipation. In KiCad, create a copper zone on B.Cu connected to your GND net. Avoid splitting the ground plane with traces — route signals on the front layer and keep the back layer as an unbroken ground pour. This is especially important for ESP32 designs with RF signals.
How long does it take from order to receiving assembled boards?
Typical timeline for JLCPCB Economic PCBA: 1-2 hours for engineering review, 2-3 days for PCB fabrication, 2-5 days for assembly, and 7-15 days for standard shipping (3-5 days DHL Express). Total is roughly 12-25 days with standard shipping or 8-15 days with express. Rush fabrication options can reduce production time by 1-2 days for an additional fee.